The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used for example for a semiconductor device including a non-volatile memory and a method for manufacturing the same.
As an electrically writable/erasable non-volatile semiconductor storage device, an EEPROM (Electrically Erasable and Programmable Read Only Memory) has been widely used. These storage devices represented by a flash memory widely used at present include an electro-conductive floating gate electrode surrounded by an oxidized film under a gate electrode of a MISFET or a trapping insulating film, and the electric charge storage state in the floating gate or the trapping insulating film is made the storage information which is read as a threshold value of the transistor. This trapping insulating film means an insulating film capable of storing the electric charge, and a silicon nitride film and the like can be cited as an example. By charging/discharging of the electric charge to/from such an electric charge storage region, the threshold value of the MISFET is shifted, and the MISFET is operated as a storage element. As the flash memory, there is a split gate type cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film. In such memory, by using the silicon nitride film as the electric charge storage region, such advantages are provided of being excellent in reliability in holding data for discretely storing the electric charge compared to the electro-conductive floating gate film, being capable of thinning the oxide films over and below the silicon nitride film because of the excellent reliability in holding data, being capable of lowering the voltage of the writing/erasing operation, and so on.
Also, the memory cell includes a control gate electrode (selection gate electrode) that is formed over a semiconductor substrate through a first gate insulating film, a memory gate electrode that is formed over the semiconductor substrate through a second gate insulating film including an electric charge storage region, and a pair of semiconductor regions (a source region and a drain region) that are formed over the surface of the semiconductor substrate so as to sandwich the control gate electrode and the memory gate electrode. In the memory cell region, plural memory cells are disposed in a matrix shape in the X-direction and the Y-direction. For example, with respect to plural memory cells arrayed in a row in the Y-direction, the control gate electrode and the memory gate electrode are respectively formed integrally, and the control gate electrode and the memory gate electrode extend in the Y-direction. For example, the control gate electrode and the memory gate electrode comprised of a polycrystalline silicon film and the like extend to an electric supply region (shunt region) adjacent to the memory cell region, and are coupled there with a control gate line (selection gate line) and a memory gate line which are comprised of a metal wiring layer for example.
In Japanese Unexamined Patent Application Publication No. 2006-049737, Japanese Unexamined Patent Application Publication No. 2011-222938, and Japanese Unexamined Patent Application Publication No. 2006-054292, technologies on a shunt structure for coupling the control gate electrode with the control gate line and coupling the memory gate electrode with the memory gate line in the electric supply region are described.